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| sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 1 features ? 4.5v 30v input step down converter ? built-in feedback compensation with feed forward ? overcurrent circuit protection with auto-restart using fet rdson sensing ? 300khz fixed switching frequency ? external synchronization capable ? up to 30a output capability ? highly integrated design, minimal components ? uvlo detects both v cc and v in ? power good and fault output ? on-board 1 ? sink (1.5 ? source) nfet drivers ? programmable soft start ? fast transient response ? high efficiency: greater than 95% possible ? evaluation boards available to aid in design description the sp6153 has been designed to be implemented as synchronous step-down switching regulator. a complete high performance supply using type iii co mpensation can be created with as few as 11 external components. compensation has been optim ized based on output voltage and output capacitor selection. the sp6153 is designed to drive a pair of external n-channel fets using a fixed frequency, feed-forward pwm voltage mode architecture. protec tion features include uvlo, thermal shutdown, current limit using fet rdson and out put short circuit protection. typical application schematic sp6153 300khz synchronous buck controller with frequency synchronization
sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 2 absolute maximum ratings these are stress ratings only and functional oper ation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absol ute maximum rating conditions for extended periods of time may affect reliability. vcc????????????????...?????..?5.5v vin? ???????????????..???????.35v bst???????????????...????????40v bst-swn???????????...??????..??.5.5v swn???????????...?????..???-2v to 35v gh?????????????????. -0.3v to bst+0.3v gh-swn????????????.?????..???.5.5v all other pins?????????????-0.3v to vcc+0.3v peak output current < 10us gh,gl?????? ???... 2a storage temperature?????.?.????-65 c to 150 c power dissipation???????????????.??..1w lead temperature (soldering, 10 sec)?????..??300 c esd rating??? ?+/-1kv uvin, +/-2kv all other pins hbm uvin to vin????????????????????.1kv thermal resistance jc ?????..????????..5 o c/w electrical specifications: (unless otherwise specified) -40 c< tj< 125 c, 4.5v sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 4 output: nfet gate drivers parameter min typ max units conditions gh & gl rise times 35 ns gh & gl fall times 30 ns gl,gh pull-down resistance 1 ? gl,gh pull-up resistance 1.5 ? gl to gh non overlap time 35 50 ? ns gh & gl measured at 2.0v swn to gl non overlap time 20 30 ? ns measured swn = 100mv to gl = 2.0v gh & gl pull down resistance 50 k ? block diagram sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 5 pin description pin # pin name description 1 en enable pin - pulling this pin below 2.5v will stop t he part from switching, below 0.4v will place the ic into sleep mode. this pin is internally pul led to vcc with 1ua current source. this pin is ignored when the internal fault flag is set. w hen fault flag is cleared en pin will return to normal function with 10us delay. 2 ss soft start pin. connect an external capacitor between ss and gnd to set the soft start rate based on the 10ua source current. the ss pin is held low via a 1ma (min) current during all fault conditions. the output rise time is dictated by the time the soft star t pin takes to rise to 0.6volts. the pin will continue to rise to 5v allowing easy implementation of sequential, ratiometric, and simultaneous (output tr acking) power up protocols. see anp6. 3 gl high current driver output for the low side nfet swit ch. it is always low if gh is high or during a fault. 4 gnd ?power? ground pin. connect this pin as close as possible to the low-side fet source. 5 vfb feedback voltage and short circuit detection pin. it is the inverting input of the error amplifier and serves as the output voltage feedback point fo r the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. whenever vfb drops 0.25v below the positive reference, a short circuit fault is detected and the ic enters hiccup mode. 6 vout connect to converter output voltage. 7 vcc output of the internal 5v linear regulator or bi as supply input. if external bias supply is used connect to the voltage between 4.5v and 5.5v. 8 uvin uvlo input for vin voltage. internal resistor divider connected between vin and uvin sets uvlo threshold at 8.5v. to adjust the threshol d connect an external resistor divider ? see applications section. 9 bst high side driver supply pin. connect bst to the ex ternal boost diode and capacitor as shown in the typical application circuit on page 1.the high side driver is connected between bst pin and swn pin and delivers the bst pin voltage to the high side gate each cycle. 10 vin connect input voltage supply to this pin. 11 gh high current driver output for the high side nfet switch. it is always low if gl is high or during a fault. 12 swn lower supply rail for the gh high-side gate driver. connect this pin to the switching node at the junction between the two external power mosfet transistors. this point is also the input to the internal ocp comparator. the voltage across the low side fet(s) is measured each cycle and compared to a 150mv reference. see the applicat ions section on how to calculate the ocp level. 13 sout sync output. this pin can be used to synchronize two pwm controllers. the output is a logic level pulse train at the converter switching frequency. the pulses are approximately 50% duty cycle regardless of the c onverters present duty cycle. the rising edge of this pulse correspond with the rising edge of the high side gate (gateh) pulse 14 sin sync input. this pin serves as an input for synchronization pulses and can be used to ensure the supply will operate with a set phase in relation to another signal. the input signal should not exceed the controller vcc. it can range from 10% to 90% duty cycle and remain synchronized. the sin signal must be within +/- 15% of the internal oscillator. the gl(high) signal will always be in phase with the connected sin(high) signal. example: to maintain out of phase operation a signal that corresponds with the gh of supp ly 1 should be connected to sin of supply 2. note: when not used tie sin to gnd 15 pwrgd power good output. this open drain output is pulled low when vout is outside of the regulation. connect an external resistor to pull high. when the output reaches regulation this output transitions high after a pre-set 200ms delay. this pin is internally pulled to vcc with 2.5ua current source. 16 flt fault flag. this is an open-drain output that trans itions low when the internal fault is detected. this pin is internally pulled to vcc with 2.5ua current source. pad agnd analog ground pin. the controller vcc and logic are referenced to this pin. sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 6 general overview the sp6153 is a fixed frequency, voltage mode, synchronous pwm controller optimized for high efficiency. the part has been designed to be especially attractive for single supply input voltages ranging between 5v and 30v. the heart of the sp6153 is a wide bandwidth transconductance amplifier designed to ac- commodate a type iii compensation scheme. a precision 0.6v reference present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.6v via the vfb pin. the output of the error amplifier is internally compared to a feed- forward ( vin/5 pk-pk) ramp and generates the pwm control. timing is governed by an internal oscillator that sets th e pwm frequency at 300 khz. the sp6153 contains several unique control features that are very powerful in distributed applications. first, non-synchronous driver control is enabled during startup to prohibit the low side switch from pulling down the output until the high side switch has attempted to turn on. programmable vin uvlo allows the user to set the exact value at which the conversion voltage can safely begin down-conversion, and an internal vcc uvlo which ensures that the controller itself has enough voltage to properly operate. by using the softstart pin alone to control start-up ramp time or the softstart and enable pin can be used to create unique sequencing configurations. sp6153 has type-iii internal compensation for use with electrolytic/tantalum or ceramic output capacitors. the controllers internal 2a fet drivers are capable of driving fets selected for output currents up to 30 amps. ocp is accomplished be measuring the voltage across the low side fet(s) each cycle. this voltage/(fet rdson) represent the current through the device. the voltage is compared to a 130mv reference and if exceeded a complete restart of the controller is initiated repeatedly until the current level de creases (?hiccup? mode) see the applications section on how to calculate the ocp level. other protection features include thermal shutdown and short-circuit detection. in the event that either a thermal, short-circuit, or uvlo fault is detected, the sp6153 is forced into an idle state where the output drivers are held off for a finite period before a restart is attempted. a thermal pad on the bottom of the qfn package ensures the controller remains cool even when driving large fets. soft start ?soft start? is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. in a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. as a result, excess source current can be defined as the current required to charge the output capacitor. ? the sp6153 provides the user with the option to program the soft start rate by tying a capacitor from the ss pin to gnd. the selection of this capacitor is based on the 10a pull up current present at the ss pin and the 0.6v reference voltage. therefore, t he excess source can be redefined as: a typical start-up time of approximately 5ms (vout = 0 to vout nominal) can be achieved by using a 47nf capacitor on the soft start pin. under voltage lock out (uvlo) the sp6153 has two separate uvlo com- parators to monitor the bias (vcc) and input (vin) voltages independently. the vcc uvlo is internally set to 4.2v. the vin uvlo is programmable through uvin pin. when uvin pin is greater than 2.5v the sp6153 is permitted to start up pending the removal of all other faults. a pair of internal resistors is connected to uvin as shown in the figure below. sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 7 internal and external bias of uvin without external biasing the vin start threshold is 8.5v. a small capacitor may be required between uvin and gnd to filter out noise. for applications with vin of 5v or 3.3v, connect uvin directly to vin. to program the vin start threshold, use a pair of external resistors as shown. external resistors should be in the order of one to ten thousand ohms. this will ensure they are an order magnitude smaller than internal resistors. the vin start threshold is given by: for example, if it is required to have a vin start threshold of 7v, then let r8 = 5k ? and using the vin start threshold equation we get r5= 9.09k ? thermal and short-circuit protection because the sp6153 is designed to drive large output current, there is a chance that the controller could become too hot. therefore, an internal thermal shutdown (145c) has been included to prevent the ic from malfunctioning at extreme temperatures. when the ic temperature returns to 10 degrees below the shutdown temperature (typically 135c) the ic will begin operation again with a normal soft-start. a short-circuit detection comparator has also been included in the sp6153 to protect against an accidental short at the output of the power converter. this protec tion feature operates separately from the ov er current protection circuitry. a comparator constantly monitors the positive and negative terminals of the error amplifier, and if the vfb pin falls more than 250mv (typical) below the positive reference, a short-circuit fault is set. because the ss pin overrides the internal 0.6v reference during soft start, the sp6153 is capable of detecting short- circuit faults throughout the duration of soft start as well as in regular operation. power good and fault power good output: this open drain output is pulled low when vout is outside of regulation. connect an external resistor to pull high. when the output reaches r egulation this output transitions high after a pre-set 200ms delay. this pin is internally pulled to vcc with 2.5ua current source. the fault pin is an open-drain output that transitions low when the internal fault is detected. when multiple sp6153s are used together fault pins can be connected together and applied to all enable inputs to ensure that under fault condition all converters turn-off and re-start with correct sequence. this pin is internally pulled to vcc with 2.5ua current source. over current protection and fet selection select the power mosfet (s) for voltage rating v (br) dss, on resistance: rdson, and thermal resistance r thja . the mosfet voltage rating v (br) dss should be about 1.25 x vin in order to guard against switching transients. a higher or lower rating may be concluded once mosfet performance is characterized in circuit. rdson should be selected such that when operating at peak current and junction temperature the overcurrent trip voltage of the sp6153 is not exceeded. allowing 50% for temperature coefficient of rdson and 15% for inductor current ripple, the following expression can be used as a quick selection reference: more than one mosfet may be required to meet the rdson requirement. within this constraint, selecting mosfets with lower rdson will reduce conduction losses at the expense of increased switching losses. as a rule of thumb select the highest rdson mosfet that meets the above criteria as a rough guide switching losses can be assumed to equal the conduction losses. a simplified expression for conduction losses is given by: (note iout would be divided by number of fets if >1) or sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 8 then the mosfets junction temperature can be estimated from: over current protecti on is accomplished by comparing the voltage across the low side mosfet(s) when fully on, to a fixed 150mv reference after a pre-set blanking time of ~120ns. the mosfet voltage is measured at the swn pin. this voltage represents the current through the device(s) at that point in time by ohms law. a quick estimate of the current trip point can be calculated by dividing the voltage trip level by the fet rdson. divide the fet resistance by the number of fets in use. however, in a dc-dc buck converter the inductor current is saw tooth in shape as it is charged and discharged linearly each cycle. to understand the exact trip point of your converter it is important to consider the inductor current ripple, this may be high if you are designing a wide input range converter and you are considering the entire vin range. the mosfet current is measured at a minimum of 120ns after the gate low signal has gone high (fet is on) and as a result it is very close to the peak current in the inductor. the peak inductor current varies with the amount of inductance used, the input and output voltage, as well as the converter frequency; therefore it is necessary to consider these variables when calculating the converter current limit. when the low side gate signal is high, the fet(s) is on. it is during this time the fet voltage must be sampled to measure the current. buck converter waveforms showing fet measurement area the box shows the mesurement window (not to scale) after a 120ns minimum delay. if we were to zoom in to the region around the mesurement window we would see the reason for the measurement delay as illustrated below. to ensure both the high and low side fet are never on at the same time there is a built in ?non-overlap time? to the fet driver. this is a short period (35ns typical) where neither fet is on. during this time the low side fet intrinsic or body diode will conduct briefly. the intrinsic diode has a forward voltage that is much higher than the voltage drop caused by the fet rdson as shown below. it is not desired to measure the current during this time. note that the voltage across the low side fet while conducting is negative. it is this negative voltage that is measured by the controller. buck converter waveforms showing fet measurement area and swn level in detail the inductor peak current can be calculated using the following formula: the peak fet voltage drop is then swn gate high gate low inductor current 120ns measurement window swn gate high gate low ch2 ground 120ns from gl high non-overlap time/diode measurement area sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 9 for the fet rdson value it is important to consider how many fets are in use, the fet resistance at the temperature you are operating at, the fet resistance at the gate drive voltage you are using (use the 4.5v worst case level) and any trace resistance between the fets and the meauring points that would generate any signifigant voltage drop. the ocp trip voltage is not adjustable. however, the 150mv trip level should typically provide the user with a nominal 150% over current trip point when using fets that have been selected to provide a good performance and size balance for the application. users designing with maximum efficiency as their only goal and who are using fets well below their current ratings could find the current limit higher than the 150% nominal level. boost pin connect a 0.047 f low-esr ceramic capacitor between the bst pin and swn pin. the high- side mosfet gate drive voltage is provided by this capacitor. type x7r or x5r are recommended due to their stable values over temperature. to obtain the vin+vcc voltage the high-side fet gate requires to turn on, a boost diode is required to be connected from vcc to the bst pin. select a part that is rated to a minimum of vin and an average current rating of 20ma. a series resistor referred to as a ?boost resistor? is sometimes required to slow switching slightly and reduce circuit noise. (see application schematic for resistor placement in circuit) in particular for high current or high vin designs, it is helpful to place this resistor in case it is required. if the design meets performance specification without it, it can be shorted or removed. setting the output voltage the output voltage can be programmed by using a voltage divider on the output. because the compensation is internal, an r1 of 332k ? must be used. set the output voltage using the following equation: input capacitor selection the input capacitance should be selected to maintain a minimum input ripple of approximately 300mv. check the capacitance versus operating voltage ratings for the ceramic capacitors selected. very significant reductions in capacitance can be seen when used above 1/3 the rated voltage. output inductor and output capacitor selection with example the 6153 has a built in type iii compensation. this saves valuable board space and still allows for the use of high performance - low esr ceramic output capacitors. however, because the compensation is fixed certain guidelines must be followed to yield a stable design. if you have experience designing a dc-dc converter with type iii compensation use the internal compensation values shown below in your design calculations and simulations. 6153 internal compensation components alternatively the following simplified design procedure can be used. the equations are derived from the standard buck converter model containing the modulator, output filter, and compensation network. basic buck converter control model - + rz2 = 130k ? vref (0.6volts) r1 (external) = 332k ? rz3 = 18k ? cz3 = 50p f l/c output filter compensation modulator sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 10 the equations in this simplified approach account for the ramp and input voltage, the location of the lc double pole and the location of the output capacitor esr zero. they will ensure there is adequate phase boost at the converter cross-over frequency to provide stable operation. other assumptions that were made generating the simplified equations include: i) the converter bandwidth will be approximately 30khz ii) cz2 was selected by placing a zero from the compensation network at 50% of the output filter double pole frequency iii) cp1 was calculated by placing the first pole at the esr zero frequency iv) rz3 and cz3 were selected so that the second pole is at ? the switching frequency and the second zero is set at the output filter double pole step 1 : calculate the required output inductance: where the ripple% is usually 30 to 40% of the maximum output current. for example: for 40% ripple, ripple% would be equal to ?0.4?. in general, a higher ripple % will mean a lower inductance, smaller inductor and a faster transient response but higher output voltage ripple. for a 5v to 1.8vout design at 20amps we calculate: step 2 : output capacitor selection the output capacitor contributes two parts of the control equation, the actual output capacitance and the capacitor esr. the calculated target output capacitance will guarantee a stable solution, however, a significant amount of variation can be tolerated because of the conservative design procedure implemented. a final c out total of -50% to +300% can be tolerated. when it is desired to use a c out value beyond these limits the supply should first be simulated for stability. calculate the target output capacitance from: from our example above we calculate: the supply also has a load transient requirement. with a 10 amp load transient the supply output is required not exceed a 2% voltage deviation. the capacitance required to maintain the output to this level is calculated by: where ? v out is the voltage deviation, d max is the maximum converter duty cycle, in this case 90%, use 0.9. continuing with our example the c out requirement for transient will be: we will select 300uf for our output capacitance. next we calculate the target output capacitor esr. remember that paralleling capacitors also parallels the capacitor esr. from out example this calculates to: the same considerations apply to this target output capacitor esr. a final output capacitor esr total that is -50% to +300% can be tolerated without concern. 3 x 100uf ceramic capacitors will be selected. the murata part number grm31cr60j107m is suitable. at 300khz each capacitor has an esr of approximately 5m ? , giving a total output esr of approximately 1.6m ? . the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 11 where i pk-pk is defined by layout the sp6153 uses two sets of critical components: switching power components and the small signal components. the essential small signal components are those connected to susceptible nodes or those supplying critical bias currents. the switching power components are most important from a layout point of view because they switch a large amount of energy and tend to produce a large amount of electrical noise. a multi-layer printed circuit board is recommended. layout considerations a) create a separate small analog ground plane near or under the ic. connect the signal ground center pad to this plane. small signal grounding paths including feedback resistors, soft start capacitor, should be connected to this signal ground plane. b) the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. connect the vout pin as close as possible to the load. c) route all high speed switching nodes away from the control circuitry. d) place the high side fet source as close as possible to the low side fet drain. e) place the pwm controller ic close to lower fet. the gl connection should be short and wide. the ic can be best placed over a quiet ground area. avoid switching ground loop current in this area. f) the upper fet, lower fet, input capacitors, inductor and output capacitor, should be placed first. isolate these power components on the topside of the board with their ground terminals adjacent to one another. place the input ceramic capacitor(s) very close to the mosfets. g) keep the loop formed by input capacitor, the top fet and the bottom fet as small as possible. h) insure the current paths from the input capacitor to the mosfet; to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. i) place the gate drive components boost capacitors and boost diode together near the sp6153 ic. j) use wide but short traces or if possible, copper filled polygons to connect the junction of upper fet, lower fet and output inductor. k) do not unnecessarily oversize the copper islands for swn/lx node. since the swn node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. l) ensure the feedback connection to output capacitor is as short and direct as possible for more detail on the 6153 layout see the sp6153evb (evaluation board) manual available on our web site. each layer is shown in detail as well as a complete bill of materials and performance characterization. starting at the top left, the areas noted are as follows: input capacitors, mosfets, output inductor, output capacitance, and controller ic. 6153 evaluation board screen shot the sp6153 evaluation board was created to test and evaluate up to a 30 amp supply. significant copper has been used as well as multiple parallel vias to reduce copper resistance and aid in the cooling of circuit cin fets lout cout 6153 sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 12 components. this evaluation board can be ordered through our web site. applications information schematic: sp6153 configured as a 5vin nominal to 1.8v/20 amps dc-dc converter. sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 13 applications information performance waveforms lx node & output ripple voltage output load short circuit startup into full load 20a startup into no load lx node output ripple vin=5v, iout=20a vout iout: 10a/div vin=5v softstart vin vin=5v vout softstart vin output ilx: 25a/div softstart sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 14 device bonding / pin out sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 15 ordering information part number temperature range package sp6153er1l???????????????. -40 o c to +125 o c ?????????????.?.16 pin qfn sp6153er1l/tr??????.???????. -40 o c to +125 o c ??????.????????..16 pin qfn all available parts are lead free sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 16 package 16pin qfn 4x4mm sp6153 6153 wide input voltage range pwm controller ? copyright 2008 exar corporation 2/06/08 17 4mm |
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